This application claims priority to UK Application No. 0706049.4 filed Mar. 28, 2007, the entire content of which is hereby incorporated by reference.
1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to data processing systems having low leakage power modes of operation.
2. Description of the Prior Art
In many circuits, particularly those that run off remote power supplies such as batteries, it is important to keep the power consumption of the circuits low. As well as addressing the issue of operational circuit efficiency, attention is also being turned to reducing static power consumption, i.e. power loss due to leakage currents. Power savings can be achieved by providing a circuit with low power modes, or sleep modes. In some of these modes the power is turned off to the circuit so that no power is consumed. Although this is very power efficient there are issues with the state being lost and with the restoration of this state when the circuit is powered up. There are also low power modes where the system is simply halted and the clock is turned off. In such circumstances data is not lost. Often a system may go to a halted mode first where the clock is switched off and thus, the state of each circuit element is held at that value. Steps are then taken to store the state required in various retention latches prior to moving to a fully powered down state.
It has been found that leakage power in the halted mode is highly state dependent. However, the architectural or micro-architectural state at which a CPU (or any IP block for that matter) is halted is not controlled as such but is the state that the CPU is in at the point a wait-for interrupt or external hardware control signal is received.
For example, there may be a set of registers that are implemented as standard cells with standard cell logic between the register stages. This standard cell logic is combinatorial logic and can leak power, but this leakage power is dependent on the values output from the register cells (sequential logic). Thus, there is theoretically a set of state bits that would minimise the leakage of the combinatorial logic located between the sequential logic stages. However, loading up this specific set of vectors or scanning in the state bits to produce such a state is expensive in terms of energy and time.
“Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic” by Chopra et al. Proceedings of the 17th International conference on VLSI Design, looks at power dissipation in CMOS circuitry during inactive periods, and at how this can vary with the input values at individual gates. It discloses algorithms that can be used to calculate a set of vectors to produce input values for which leakage is a minimum.
“Leakage Current Reduction in CMOS VLSI Circuits by Input Vector Control” by Abdollahi et al. IEEE Transactions on Very Large Scale Integration Systems, Vol 12m No 2, February 2004, pages 140-154 discloses shifting in a new set of external inputs and preselected internal signals into a circuit in response to a sleep signal to minimise power loss in sleep. These signals are input into the combinatorial logic and thus, may affect the data paths inside this logic.
It would be desirable to be able to reduce leakage power without interfering with the clocking paths or other critical paths of the circuitry and without spending too much power and time producing a desired state.